1. Field of the Invention
The present invention relates to a method for fabricating a dynamic random access memory (DRAM) and, more particularly, to a dynamic random access memory (DRAM) containing a capacitor on bit line (COB) type memory cells and its fabrication method.
2. Discussion of the Related Art
A metal-oxide-semiconductor (MOS) type DRAM has a memory cell comprising one MOS transistor and one capacitor connected thereto. As developments have been made in DRAM device technique to achieve high integration and high speed response, a size of each capacitor has been reduced, resulting in the amount of charge stored in the capacitor being decreased. The decrease in the amount of charge results in soft errors that may alter the content of the memory cell. To overcome this problem, a method for increasing the occupied area of each capacitor has been proposed, in which storage nodes composed of polycrystalline silicon are formed in a semiconductor substrate in order to increase capacitance of the capacitor.
FIG. 1 is a plan view of a memory cell array of a DRAM according to a related art. As shown in FIG. 1, on the surface of a semiconductor substrate 1 are formed a plurality of word lines 17a, 17b, 17c and 17d which run parallel with one another in rows. Also formed on the substrate are a plurality of bit lines 55 which run parallel with one another in columns. A plurality of memory cells (MC) are arranged at the respective intersections of the word lines and the bit lines. Each memory cell comprises one transfer gate transistor 53 and one capacitor 64. The transfer gate transistor 53 comprises a pair of source/drain regions 46 formed in the surface of the semiconductor substrate 1, and a gate electrode (word line) 17b or 17c formed between the source/drain regions 46. A thick insulation layer is formed on the gate electrodes 17b and 17c. Subsequently, contact holes 28 and 29 are formed in a predetermined portion of the insulation layer so as to expose the source/drain regions 46 of the transfer gate transistor 53.
The reference numeral 29 denotes capacitor node contact portions, and the reference numeral 28 denotes a bit line contact portion. The contact holes 28 and 29 formed by photolithography and the etching method are gap-filled with the plug of a conductive layer such as a doped polycrystalline silicon layer. A bit line contact hole 91 is located over an element isolating insulation layer. In the memory cell array, the word lines have a predetermined width and arranged in parallel with a predetermined spacing from one another.
Now, manufacturing steps of the DRAM memory cell shown in FIG. 1 will be described with reference to sectional views of FIGS. 2A to 2L, which are views along line I-I' of FIG. 1.
As shown in FIG. 2A, an element isolating insulation layer 11 and a channel stopper region (not shown) are formed in predetermined regions on the main surface of a P-type semiconductor substrate 1. A gate insulation layer 15, a polycrystalline silicon layer 17 and an interlayer insulation layer 19a are sequentially formed on the surface of the semiconductor substrate 1.
The element isolating insulation layer 11 may be formed by a selective oxidation method such as a LOCOS (Local Oxidation of Silicon) method or other methods including STI (Shallow Trench Isolation). The gate insulation layer 15 is formed by the thermal oxidation method. The polycrystalline silicon layer 17 and the interlayer insulation layer 19a are each deposited to a thickness of 1000-2000 .ANG. by the CVD method.
As shown in FIG. 2B, word lines 17a, 17b, 17c and 17d are formed by photolithography and the etching method. The interlayer insulation layer 19a of the patterned oxide film is left on the surface of the word lines 17a-17d.
As shown in FIG. 2C, an insulation layer is formed on the whole surface of the semiconductor substrate 1 by the CVD method and etched by an anisotropical reactive ion etching (RIE) to form sidewall spacers 20 on the peripheries of the word lines 17a-17d. Impurity ions 40 such as arsenic are implanted under an implantation energy 30 KeV at a dose of 4.0.times.10.sup.15 /cm.sup.2 in the surface of the silicon substrate 1 by using the word lines 17a-17d covered with the insulation layer 19a and the spacers 20 as masks to form the source and drain regions 46 of the transfer gate transistor.
As shown in FIG. 2D, the surface of the semiconductor substrate 1 is planarized with an interlayer insulation layer 26a, e.g., a BPSG (Borophosphrousilicate Glass) film. Contact holes 33 are formed in the bit line contact portion 28 and the capacitor node contact portion 29 by photolithography and the etching method, which is followed by deposition of doped polycrystalline silicon. Then, polysilicon plugs 28 and 29 are formed in the contact holes by an etch-back method.
The plugs may be formed not only by the etch-back technique using the RIE but also by other methods including CMP (Chemical Mechanical Polishing). The interlayer insulation layer 19a on the word lines and the sidewall spacer 20 on the peripheries of the word lines are integrally called an interlayer insulation layer 24.
As shown in FIG. 2E, an insulation layer 61 is deposited on the whole surface of the semiconductor substrate 1, isolating the plugs 28 and 29. Contact holes (not shown) are formed over the bit line contact portion 28. A conductive layer, such as a doped polycrystalline silicon layer, a metal layer, or a metal silicide layer, are formed on the surface of the semiconductor substrate 1, which are patterned by photolithography and the etching method. As a result, the bit lines (not shown) are formed.
Subsequently, an etching stopping layer 63, such as a nitride (Si.sub.3 N.sub.4) film having a thickness of more than 100 .ANG., is formed. Then, a silicon oxide (SiO.sub.2) film 65a having a thickness of more than 5000 .ANG. is formed on the surface of the nitride film 63.
The bit lines are disposed above the element isolating insulation layer of the memory cell array and in the direction perpendicular to the word lines. The bit lines are also arranged in parallel with the active regions of the memory cell, each having two transfer gate transistors as MOS transistors. The interlayer insulation layers 24 and 26a are integrally called an interlayer insulation layer 27.
As shown in FIG. 2F, a capacitor isolating layer 65 for isolating the adjacent capacitors is formed by patterning the oxide film 65a by the etching method. The selective etching ratio of the nitride film 63, which is an etching stopping layer, to the oxide film 65a is extremely high. Therefore, in this etching step, the nitride film 63 is etched at a much slower rate than the oxide film 65a.
As shown in FIG. 2G, contact holes 70 are formed so as to reach the plug of the capacitor node contact portion 29 on the source and drain regions 46 by photolithography and the etching method.
As shown in FIG. 2H, a polycrystalline silicon layer 72 having a thickness of 500-1500 .ANG. is deposited on an inner surface of the contact hole 70, on the surface of the nitride film 63, and on the surface of the capacitor isolating layer 65 by the CVD method. Then, a thick resist 75 is applied over a surface of the polycrystalline silicon layer 72.
As shown in FIG. 21, the resist 75 is etched back to expose a part of the polycrystalline silicon layer 72.
As shown in FIG. 2J, the exposed surface of the polycrystalline silicon layer 72 is selectively removed by anisotropic etch or the like. As a result, the polycrystalline silicon layer 72 is isolated on the surface of the capacitor isolating layer 65 to form a lower electrode 80 of the capacitor.
As shown in FIG. 2K, the resist 75 is removed by the etching method, and the capacitor isolating layer 65 is removed by a plasma etching method. Then, a dielectric layer 84, such as a nitride film, is formed on the surface of the lower electrode 80.
As shown in FIG. 2L, an upper electrode 85 is formed of a polycrystalline silicon layer having a thickness of 2000-3000 .ANG. on the surface of the dielectric layer 84 by the CVD method. Thereafter, an insulation layer 88 and an interconnection layer 90 are formed to complete the manufacturing steps of the memory cell of the DRAM.
In the memory cell of the DRAM according to the related art, the plugs used as the capacitor and bit line contacts are formed in the source and drain regions of the transfer gate transistor by photolithography and the etching method after the word lines are formed. These patterns are arranged linearly between the transfer gates, thereby requiring the transfer gates to be spaced farther apart than is otherwise desired to provide ample room between transfer gates for making desired contacts to active areas. Such increase in transfer gate pitch works against the integration of the memory cell. In addition, during deposition of an insulation layer for isolating the word lines after the spacer is formed on the peripheries of the word lines, key holes may be formed inside the insulation layer and adversely affect the subsequent manufacturing process steps.